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Chapter 26: Design Examples
Farrow Based Resampler
Open this model
This design example illustrates how to implement a Farrow based decimating sample
rate converter.
Many integrated systems, such as software defined radios (SDR), require you to
resample data so that a unit can comply with communication standards where the
sample rates are different. In some cases, where one clock rate is a simple integer
multiple of another clock rate, use interpolating and decimating FIR filters to
accomplish resampling. However, in most cases the interpolation and decimation
factors are so high that this approach is impractical.
Farrow resamplers provide an efficient way to resample a data stream at a different
sample rate. The underlying principle is that the phase difference between the current
input and wanted output is determined on a sample by sample basis. This phase
difference then combines the phases of a polyphase filter in such a way that a sample
for the output phase, which you want, generates.
This design example illustrates a Farrow resampler. You can simulate its performance
in MATLAB, change it as required for your application, generate VHDL and
synthesize the model to Altera devices. The design example has an input clock rate
identical to the system clock. For applications where the input rate is much lower than
the system clock, time sharing should be implemented to achieve a cost effective
solution.
The example model is FarrowResamp.mdl .
f For more information about this design, click on the Doc symbol in the design model
window.
CORDIC, 20 bits Rotation Mode
Open this model
This design example illustrates an iterative 20 bit rotation mode, which computes sine
and cosine angles and implements with the coordinate rotation digital computer
(CORDIC) algorithm.
The example model is DemoCordic.mdl .
Imaging Edge Detection
Open this model
This design example illustrates an edge detection design.
The example model is Edge_detector.mdl .
f Refer to AN364: Edge Detection Reference Design for a full description of the edge
detector design.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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